GROSHEC: Is the processor for rough set methods in sight?

The rough sets’ theory developed in the eighties of the twentieth century by Prof. Z. Pawlak is an useful tool for data analysis. Therefore a lot of rough sets algorithms were implemented in scientific and commercial tools for data processing. But data processing efficiency problem is arising with increase of the amount of data. Software limitations led to searching the new possibilities. Field Programmable Gate Arrays (FPGAs) are the digital integrated circuits which function is not determined during the manufacturing process, but can be programmed by engineer any time. One of the main features of FPGAs is the possibility of evaluating any boolean function. That’s why they can be used for supporting rough sets calculations. At the moment there are some hardware implementation of specific rough set methods. Detailed summary can be found in [1] and in [6]. None of the above are the complex solutions as they are only implementations of the specific rough sets method. Authors propose the fully operational Systemon-Chip (SoC) named GROSHEC (General ROugh Set Hardware Enhanced Computer) based on Altera NIOS II core. SoC was implemented in Altera’s Stratix III FPGA using TerasIC DE3 development board. Some details on previous authors’ work can be found in [5, 2, 3].